Contemporary video compression algorithms require significant memory bandwidth for referencing previously decoded pictures. A decoder memory buffer is used to maintain a number of previously decoded image frames ready for display so these frames can be used as references in decoding other image frames. Due to the development and availability of high definition video, the rate at which the data in the decoder memory buffers are transferred has increased. In addition, the memory buffer typically provides data blocks that are substantially larger than that required by the decoder to process a particular image block, thereby increasing the memory bandwidth without benefit.
In some decoder systems motion prediction (MP) caches are used to limit the data transfer rate from the memory buffer. An MP cache stores image pixel values for previously decoded macroblocks that may be useful for subsequent macroblocks to be decoded. An MP cache is typically limited in capacity and expensive in comparison to a decoder memory buffer. An MP cache typically includes only a small portion of the pixel data necessary for a single video frame. Consequently, data in an MP cache are quickly replaced as new macroblocks or parts of macroblocks are written to the cache. The data replacement can be random or a least recently used (LRU) algorithm can be employed. The MP cache may be directly mapped based on one or more of memory address, image coordinates and other parameters. Cache thrashing occurs when two or more data items that are frequently needed both map to the same cache address. Each time one of the items is written to the cache, the other needed item is overwritten, causing cache misses during subsequent processing and limiting data reuse.
What is needed is a method for significantly reducing the data transfer rate from the decoder transfer buffer. The present invention satisfies this need and provides additional advantages.